Silicon-based nanoscale resistive device with adjustable resistance

ABSTRACT

A non-volatile solid state resistive device that includes a first electrode, a p-type poly-silicon second electrode, and a non-crystalline silicon nanostructure electrically connected between the electrodes. The nanostructure has a resistance that is adjustable in response to a voltage being applied to the nanostructure via the electrodes. The nanostructure can be formed as a nanopillar embedded in an insulating layer located between the electrodes. The first electrode can be a silver or other electrically conductive metal electrode. A third (metal) electrode can be connected to the p-type poly-silicon second electrode at a location adjacent the nanostructure to permit connection of the two metal electrodes to other circuitry. The resistive device can be used as a unit memory cell of a digital non-volatile memory device to store one or more bits of digital data by varying its resistance between two or more values.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Provisional Application No.61/103,928 filed Oct. 8, 2008, the contents of which are herebyincorporated by reference.

TECHNICAL FIELD

The invention relates to two-terminal non-volatile solid state resistivedevices having an adjustable resistance that can be used for memorystorage and controllable circuit interconnects.

BACKGROUND OF THE INVENTION

Resistive random-access memories (RRAMs) have generated significantinterest recently as a potential candidate for ultra-high densitynon-volatile information storage. A typical RRAM device consists of aninsulator layer sandwiched between a pair of electrodes and exhibitselectrical pulse induced hysteretic resistance switching effects. Theresistance switching has been explained by the formation of conductivefilaments inside the insulator due to Joule heating and electrochemicalprocesses in binary oxides (e.g. NiO and TiO₂) or redox processes forionic conductors including oxides, chalcogenides and polymers.Resistance switching has also been explained by field-assisted diffusionof ions in TiO₂ and amorphous silicon (a-Si) films.

In the case of a-Si structures, voltage-induced diffusion of metal ionsinto the silicon leads to the formation of conductive filaments thatreduce the resistance of the a-Si structure. These filaments remainafter the biasing voltage is removed, thereby giving the device itsnon-volatile characteristic, and they can be removed by reversediffusion of the ions back to the metal electrode under the motive forceof a reverse polarity applied voltage.

Resistive devices formed by an a-Si structure sandwiched between twometal electrodes have been shown to exhibit this controllable resistivecharacteristic. However, such devices typically have micron sizedfilaments which may prevent them from being scaled down to the sub-100nanometer range. Such devices may also require high forming voltagesthat can lead to device damage and can limit production yields.

SUMMARY OF THE INVENTION

In accordance with one aspect of the invention, there is provided anon-volatile solid state resistive device, comprising a first electrode,a p-type silicon second electrode, and a non-crystalline siliconnanostructure electrically connected between the electrodes. Thenanostructure has a resistance that is adjustable in response to avoltage being applied to the nanostructure via the electrodes. Thenon-crystalline silicon nanostructure can be, for example, an amorphoussilicon nanostructure or an amorphous poly-silicon nanostructure.

In accordance with another aspect of the invention, the resistive deviceis used as a memory cell in a digital non-volatile memory device. Thememory device can include an array of such resistive devices which, inone embodiment provides a single bit of storage for each resistivedevice and, in another embodiment, provides multi-level number storagefor each resistive device so that each memory cell can store more thanone bit of data.

In accordance with another aspect of the invention, the resistive deviceis used as an electrical interconnect in an electronic circuit. Theinterconnect can be switched between at least a substantially conductiveand substantially non-conductive state.

In accordance with yet another aspect of the invention, there isprovided a non-volatile solid state resistive device, comprising a firstmetal electrode, a p-type poly-silicon electrode, an insulating layerlocated at least partially between the electrodes, an amorphous siliconstructure embedded in the insulating layer, and a second metalelectrode. The amorphous silicon structure has opposing end faces eachconnected to a different one of the electrodes. The first electrodecomprises a metal that, in the presence of an applied voltage across theelectrodes, supplies metal ions that form a filament within the siliconstructure. As a result, the silicon structure exhibits a resistance thatcan be adjusted based on the applied voltage. The second metal electrodeis in contact with the poly-silicon electrode at a location that is nomore than 100 nm from the silicon structure.

In accordance with another aspect of the invention, there is provided amethod of adjusting a non-volatile solid state switching device from anOFF state to an ON state, comprising the step of applying a voltageacross a non-crystalline silicon nanostructure, wherein the appliedvoltage has a magnitude and duration that are selected so as to achievea predetermined probability of the silicon nanostructure switching fromthe OFF state to the ON state.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred exemplary embodiments of the invention will hereinafter bedescribed in conjunction with the appended drawings, wherein likedesignations denote like elements, and wherein:

FIG. 1( a) is a diagrammatic view of one embodiment of a single cella-Si resistive device constructed in accordance with the invention;

FIG. 1( b) is an SEM image of a top view of a partially-constructed a-Sistructure such as shown in FIG. 1( a);

FIG. 1( c) is a graph showing resistance switching characteristic of atypical a-Si structure, such as shown in FIG. 1( a);

FIG. 1( d) is a waveform showing the programming response for an a-Sidevice such as shown in FIG. 1( a);

FIG. 1( e) is a waveform showing the results of endurance testing of ana-Si device such as shown in FIG. 1( a);

FIGS. 2( a)-2(c) depict histograms of the switching response of atypical a-Si device for different bias voltages;

FIG. 2( d) is a three-part diagram showing the metal ion diffusion atdifferent conductive states of an a-Si device such as shown in FIG. 1(a);

FIG. 2( e) is a graph depicting the relationship between switching timeand bias voltage for an a-Si device such as shown in FIG. 1( a);

FIG. 3( a) shows the result of programming a typical a-Si device usingdifferent series-connected control resistors or programming currentlevels controlled by other means;

FIG. 3( b) depicts the correlation between the final resistance of theprogrammed a-Si device and the selected control resistance used toprogram the device;

FIG. 3( c) is a graph of the probability of a single, discreteresistance switching event over time for a typical a-Si device whenapplying a given bias voltage without any series connected controlresistor;

FIG. 3( d) is a graph of the probability of having at least oneresistance switching event over time for a typical a-Si device whenapplying a given bias voltage without any series connected controlresistor;

FIG. 3( e) is a graph of the probability of a single, discreteresistance switching event over time for a typical a-Si device whenusing a series connected control resistor;

FIG. 4( a) is a plot of the wait time for an ON-to-OFF resistancetransition when no bias voltage is applied to an a-Si device such asshown in FIG. 1( a);

FIG. 4( b) is a graph of the wait time versus temperature;

FIG. 5 is a schematic showing a control circuit that uses controlresistors for multi-level number storage in a single a-Si device;

FIG. 6 is a plan view, partially broken away, of a memory device usinga-Si structures such as are shown in FIG. 1;

FIGS. 7-9 are diagrammatic views of different embodiments of a singlecell a-Si resistive device having a built-in diode;

FIGS. 10 and 11 are diagrammatic views of different embodiments of ana-Si resistive device with built-in diode and a field effect transistor(FET) that operates as a gate-controlled variable resistor formulti-level programming of the a-Si device; and

FIGS. 12 and 13 depict exemplary intrinsic diode characteristics for thebasic a-Si resistive device disclosed herein.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1( a) depicts a non-volatile solid state resistive device 10comprising a nanoscale a-Si structure 14 that exhibits a resistance thatcan be selectively set to various values, and reset, all usingappropriate control circuitry. Once set, the resistance value can beread using a small voltage that is sufficient in magnitude to determinethe resistance without causing it to change. Although the illustratedembodiment uses a-Si as the resistive element, it will be appreciatedthat other non-crystalline silicon (nc-Si) structures can be used, suchas amorphous poly-silicon. Thus, as used herein and in the claims,non-crystalline silicon (nc-Si) means either amorphous silicon (a-Si),amorphous poly-silicon (poly-Si) that exhibits controllable resistance,or a combination of the two. Furthermore, although much of thediscussion herein applies also to larger scale a-Si structures such asthose having one or more dimensions in the micron range, the illustratedembodiment is an a-Si nanostructure that exhibits certaincharacteristics unique to its small scale. The term nanostructure, asused herein, refers to a structure having at least two dimensions in thenanoscale range; for example, structures having a diameter or pluralcross-sectional dimensions within the general range of 0.1 to 100nanometers. This includes structures having all three spatial dimensionsin the nanoscale; for example, a cylindrical nanocolumn or nanopillarhaving a length that is on the same order as its nanoscale diameter.Nanostructures can include the various nanoscale structures known tothose skilled in the art; for example, nanotubes, nanowires, nanorods,nanocolumns, nanopillars, nanoparticles, and nanofibers. One suchstructure 14 is the embodiment depicted in FIGS. 1( a) and 1(b), whichis a plug or pillar structure that can be circular in cross-section witha diameter of less than 100 nm (e.g., 60 nm in the particular exampleshown). The pillar height or length, depending upon the orientation, canbe nanoscale (e.g., 30 nm as in the illustrated example) or larger.

The a-Si structure 14 of FIGS. 1( a) and 1(b) is embedded in aninsulating dielectric 16 which can be made of various materials andconstructed in different ways, but as shown in the figures is aspin-on-glass (SOG) layer 16 that initially is flowed around the a-Sistructure 14 and then solidified, all of which can be done using knownprocesses. The overall resistive device 10 is built up using a siliconsubstrate layer 22 that is covered by a thermal dioxide layer 24.Underlying the a-Si pillar 14 is a boron-doped or other p-typepoly-silicon electrode 18 that is in contact with a lower end face ofthe a-Si pillar 14 and that extends laterally away from the pillar toaccommodate an overlying metal electrode 20 that can be made of anysuitable metal, including, for example, a platinum group metal such aspalladium or platinum. Opposite the poly-silicon (p-Si) electrode 18 onthe upper surface (end face) of the a-Si pillar 14 is a silver (Ag)metal electrode 12 that acts as the source of filament-forming ions.Although silver is used in the illustrated embodiment, it will beunderstood that this electrode 12 (as well as the other metal electrode20) can be formed from various other suitable metals, such as gold (Au),nickel (Ni), aluminum (Al), chromium (Cr), iron (Fe), manganese (Mn),tungsten (W), vanadium (V), cobalt (Co). Other suitable metals capableof supplying filament-forming ions can be used as well.

To fabricate the a-Si device 10 of FIG. 1( a), the B-doped p-Si bottomelectrode layer 18 can be deposited by LPCVD (low pressure chemicalvapor deposition) on a prime grade silicon substrate with a 200 nmthermal dioxide. The amorphous silicon layer can be a 30 nm thick layerdeposited on top of the B-doped p-Si, followed by two RIE (reactive ionetching) steps to define the a-Si pillar 14 and the p-Si bottomelectrode 18 structures. Spin-on-glass (SOG) can then be spin coated onthe sample at a speed of 3000 RPM and then cured at 320° C. for 1 hour.This insulating SOG layer 16 provides electrical isolation of the twoopposing electrodes 12,18 as well as mechanical support for the a-Sipillar 14. After being formed, the SOG layer 16 can be partially etchedaway to create a flat surface and to expose the end face of the a-Sipillar 14. The Ag electrode 12 can then be formed on the exposed endface of the a-Si pillar 14 by patterning using a lift-off process. Thenthe second metal (platinum) electrode 20 can be applied to provide ohmiccontact to the bottom p-Si layer 18. The platinum electrode 20 islocated near the a-Si pillar 14 to help minimize resistance through thep-Si electrode 18, and this distance is preferably no more than 100 nm.The pattern design can be chosen so as to minimize the overlap betweenthe top and bottom electrodes 12,18 so as to keep a low direct leakagecurrent through the SOG 16. It will be understood by those skilled inthe art that various modifications to this fabrication procedure can bedone, and that other fabrication approaches can be used as well toachieve either the structure of FIG. 1( a) or another suitable nc-Sistructure that permits resistive adjustability of the device. U.S.Patent Application Publication No. 2009/0014707 A1 provides additionalinformation concerning the characteristics, use, and operation ofnon-volatile solid state resistive switching devices such as the a-Sidevice shown in FIGS. 1( a) and 1(b). It also provides informationconcerning the construction of an alternative embodiment of an a-Sidevice, at least some of which is applicable to the construction of thea-Si device shown in FIGS. 1( a) and 1(b). The information contained inU.S. Patent Application Publication No. 2009/0014707 A1 concerning thefabrication, construction, and use of the non-volatile solid stateresistive switching devices disclosed therein is hereby incorporated byreference.

A single a-Si device as shown in FIG. 1( a) can be used as a stand-alonereconfigurable interconnect or memory bit with its independentlycontrolled top and bottom electrode pairs. The use of chemical-vapordeposition (CVD) deposited poly-silicon as the bottom contact enablesdevice fabrication on a variety of substrates including the potentialfor multi-layered 3D structure integration. As compared with acontinuous a-Si film, the illustrated a-Si plug structure 14 helpsensure that the active a-Si region and the filament area are physicallywell defined. Furthermore, this construction of the device is fullycompatible with CMOS technology and can be readily incorporated intoexisting systems as high-density non-volatile memories or asreconfigurable interconnects in logic circuits such as neuromorphicnetworks.

FIG. 1( c) shows the resistance switching characteristics of a typicala-Si pillar such as shown in FIG. 1( a); e.g., for a device with adiameter of about 60 nm and a thickness of 30 nm. It includes an insetgraph of this switching characteristic in log scale showing the stepwisetransition during the turn-on process. High voltage forming is notrequired for these nanoscale a-Si switches and the device after formingcan be repeatedly switched between the low-resistance ON andhigh-resistance OFF states by applying positive write and negative erasevoltage pulses. The ON/OFF resistance ratio measured at small bias canbe as high as 10⁷, as indicated in FIG. 1( c). Testing of a-Si devicesfabricated in the manner discussed above have shown that, as a memorydevice, the a-Si switch exhibits excellent performance metrics in termsof yield (e.g. >95% for devices with 60 nm diameter a-Si pillars),speed, endurance and retention. FIG. 1( d) shows a representativewrite-read-erase-read pulse sequence with 50 ns write/erase pulse widthsand the output response from a typical device. Results from endurancetest of the device are shown in FIG. 1( e). A typical device withon-current <20 μA is expected to survive greater than 10⁵ programmingcycles without degradation. Beyond this limit the OFF state conductancecan start to increase, thereby resulting in a reduced ON/OFF resistanceratio.

The switching in an a-Si structure can be explained by the formation andretrieval of a nanoscale Ag filament upon the application of theprogramming voltage, schematically illustrated in FIG. 2( d). Inprevious experimental and theoretical studies on microscalemetal/a-Si/metal structures, the filament was suggested to be in theform of a series of positively charged Ag⁺ particles trapped in defectsites in the a-Si layer. The conduction mechanism in the ON state iselectron tunneling through the Ag⁺ chain and the device resistance isthen dominated by the tunneling resistance between the last Ag⁺ particleand the bottom electrode. As indicated in FIG. 1( c), this behavior isconsistent with the stepwise increase in current in log scale during theOFF-ON transition as the Ag filament grows in a step-by-step fashionwhen an additional Ag⁺ particle hops into a new trapping site.

The well-defined active switching area in the a-Si pillar structurealong with the fine control offered by the CMOS compatible fabricationprocess enables detailed studies to explore the unique characteristicsoffered by the resistive switching devices. One direct consequence ofthe filament formation model is that the switching rate will bebias-dependent, since unlike electron tunneling, the hopping of the Ag⁺particles is a thermally activated process and the rate is determined bythe bias-dependent activation energy E_(a)′(V):

Γ=1/τ=νe ^(−E) ^(a) ^(′(V)/k) ^(B) ^(T),  (1)

where k_(B) is Boltzmann's constant, T is the absolute temperature, τ isthe characteristic dwell time and ν is the attempt frequency. Asindicated in FIG. 2( d), the activation energy may be lowered by theapplication of the bias voltage, resulting in bias-dependent wait timeand switching rates.

This effect has been verified through a study of the wait time for thefirst transition (i.e., the first current step in FIG. 1( c)) as afunction of bias voltage. The wait time was measured by applying asquare pulse with a given voltage magnitude to the device in OFF stateand measuring the lapse in time t until the first sharp increase incurrent. The device was then erased by a negative voltage pulse and themeasurement was repeated. FIGS. 2( a)-(c) show the histograms of thewait time for the first transition at bias voltages of 2.6 V, 3.2 V and3.6 V on the same device. Because the stochastic nature of the switchingprocess, the wait time should follow Poisson distribution and theprobability that a switching occurs within Δt time t is given by:

$\begin{matrix}{{P(t)} = {\frac{\Delta \; t}{\tau}{^{{- t}/\tau}.}}} & (2)\end{matrix}$

The histograms in FIGS. 2( a)-(c) can be fitted to Equation 2 using τ asthe only fitting parameter, thereby yielding τ values of 15.3 ms, 1.2 msand 0.029 ms, respectively. These graphs show that τ is a strongfunction of V and decreases by almost 10³ when V is increased by only 1V. FIG. 2( e) shows the distribution of the measured τ at 5 differentbias voltages along with a fit assuming exponential decay, treating τ₀and V₀ as fitting parameters:

τ(V)=τ₀ e ^(−V/V) ⁰ ,  (3)

It is interesting to note the physical meaning of V₀ in Equation 3. FromFIG. 2( d) and to a first order, E_(a)′=E_(a)−Ed, where E_(a) is theactivation energy at zero bias, E is the electric field and d is thedistance between the Ag⁺ trapping sites. If it is assumed that most ofthe voltage is dropped across the Ag⁺ chain and the Ag⁺ particles areevenly distributed within the chain then, to a first orderE_(a)′(V)=E_(a)−V/2n, where n is the number of the Ag⁺ sites. Equation 3can then be directly derived from Equation 1, where:

τ₀=1/νe ^(E) ^(a) ^(/k) ^(B) ^(T) and V₀=2nk_(B)T.

Significantly, the V₀ value of 0.155V inferred from the fitting in FIG.2( e) is very close to that predicated by this simple model,V₀=2nk_(B)T≈0.156V, assuming there are 3 Ag⁺ sites in the filament(n=3), as suggested by the number of major current steps in the semi-logI-V plot in FIG. 1( c). Equation 3 clearly suggests that the wait timeis strongly bias dependent, and that it can be reduced exponentially byincreasing the applied bias.

The bias-dependent switching characteristics have significantimplications on the device operation. First, the switching essentiallydoes not have a “hard” threshold voltage even though the switching canbe very sharp—see FIG. 1( c), since there is always a finite probabilityfor switching to occur even at relatively low bias voltages. On theother hand, threshold voltages can be defined for a given programmingpulse width. For example, if the threshold is defined as the voltageabove which 95% success rate is achieved, then the threshold voltage is3.3V for a 1 ms pulse, and 5.1V for a 10 ns pulse width. Second,multi-level bit storage can be achieved in these devices by adjustingthe external circuit resistance. When a series-resistor is attached tothe device, the voltage across it will be reduced after the initialswitching, resulting in significantly longer wait time for thesubsequent switching events. As a result, a partially formed filamentcan be created if the programming pulse is removed before the subsequentswitching events can occur, resulting in intermediate resistance valuesbetween the ON and OFF states. FIG. 3( a) shows the final deviceresistance obtained on the same device using identical programmingpulses but with different series resistor values. The 8=2³ differentresistance levels obtained on the device suggest that each device as amemory component can store up to 3 bits of information. The deviceresistance R also correlates well with the resistance R_(S) of theseries resistor, as shown in FIG. 3( b), since the voltage dividereffect that causes the elongation of the wait time is most pronouncedwhen the device resistance becomes comparable with R_(S).

Various approaches can be used to implement the selective programming ofmulti-level numbers into the a-Si device. As used herein, a multi-levelnumber is a number having more than two (binary) levels or values, suchas a base-three digit or number, base-four number, etc. Multi-levelnumber storage can be used to store multiple bits of binary information;for example, a four-level a-Si storage cell can store two bits of binarydata in a single a-Si cell, and an eight-level cell can store three bitsof binary data. When used in a digital circuit device, the memory cellcan include a suitable control circuit to program a binary or othernumber into the a-Si device. Such circuitry is within the level of skillin the art and an exemplary diagram of one such control circuit is shownin FIG. 5. The illustrated control circuit can be used to set the a-Sistructure at any one of eight resistance levels by insertion or removalof additional resistance into the circuit in series with the a-Sistructure. For this purpose, a decoding circuit can be used to convertthree bit binary input data into the corresponding control signals usedto switch the control resistors into or out of the circuit. In this waythe decoding circuit is operable to adjust the resistance of the a-Sistructure to any of a plurality of desired resistance values by settingthe total control resistance in series with the a-Si structure to anassociated resistance value. As will be appreciated, the control circuitof FIG. 5 is diagrammatic only and specific circuit arrangements forwriting, erasing, and reading the resistance value of the a-Si structurewill be known to those skilled in the art.

A control circuit such as in FIG. 5 can be used to carry out the varioussteps discussed above for adjusting the resistance of the a-Sistructure. These steps together comprise a method that can be used toadjust the resistance of the a-Si structure between a beginningresistance value and a final resistance value. In general, the methodincludes the steps of electrically connecting the a-Si structure (whichis a first resistive device) in series with a second resistive deviceand applying a voltage across the series-connected resistive devices. Asdiscussed above, the second resistive device is a control resistancecomprising either one or a combination of two or more control resistors.The control resistance is selected (e.g., by the decoding circuit) basedon the desired final resistance value for the a-Si structure. Also, asdiscussed herein, the final resistance value of the a-Si structure canbe set at least in part based on the magnitude of the applied voltage,the duration of the applied voltage, or both. Thus, the applying stepcan comprise setting the final resistance value by applying a voltage ofa selected magnitude and duration across the series-connected resistancedevices. Furthermore, as noted above, multi-level number storage can beimplemented using the a-Si structure such that the final resistancevalue is one of a plurality of selectable resistance values. For this,the step of electrically connecting the a-Si structure in series withthe control resistance further comprises electrically forming thecontrol resistance by selectively inserting or shunting one or morecontrol resistors in series with the a-Si structure based on a chosenone of the selectable resistance values. This again can be done usingthe decoding circuit of FIG. 5 or using other suitable circuitry thatwill be apparent to those skilled in the art. To reset the a-Si deviceback to the beginning resistance value, an opposite-polarity resetvoltage is applied to the a-Si structure.

The a-Si structure can be used as a memory cell of a digitalnon-volatile memory device having a number of a-Si memory cells arrangedin an array or other suitable structure. FIG. 6 depicts an exemplaryembodiment such as could be used to form ultra-high density memorydevices. The illustrated memory device 126 includes a silicon substrate122 with a SiO₂ top layer 124 and a crossbar structure formed from a setof parallel metal electrodes 112 orthogonally overlapping a set ofparallel p-Si electrodes 118. An a-Si resistive device (generallyoutlined at 110) is located at each intersection of the two types ofelectrodes. Numbered elements of FIG. 6 differing by 100 relative tonumbered elements of FIG. 1 can have similar, although not necessarilyidentical, constructions and functions to the numbered elements ofFIG. 1. The resistive devices 110 comprise individually addressablememory cells of the memory device 126. Located between the upper set ofelectrodes 112 and the lower set of electrodes 118 is a SOG or otherinsulating layer 116 containing the a-Si structure at each memory cell110. The insulating layer 116 can extend down to the substrate's upperlayer 124 and thereby isolate adjacent electrodes 118 from each other,or a separate insulating layer 121 underneath the layer 116 can be usedfor this purpose. Also, rather than extending the p-Si electrodes 118between adjacent cells in a column, they can be restricted to each cellsite and a Pt or other suitable metal electrode can be used tointerconnect the p-Si electrodes within each column. Other variationswill become apparent to those skilled in the art. A cell size 127 forthe devices 110 is approximately 0.003 μm². In other examples, the cellsize 127 may be less than 0.003 μm² or less than or equal to 0.01 μm².

Each memory cell 110 can include a single a-Si structure and, asdiscussed above, the a-Si structure can have an adjustable resistancethat is used to implement a single bit of digital storage, or can havean adjustable resistance that is set to any of three or more resistanceseach of which corresponds to a different stored number. In this way,each memory cell is capable of multi-level number storage. For thispurpose, the memory device 126 can include a control circuit such as inFIG. 5 to permit writing of multi-level data at any selected memory cell110.

Rather than being used for bit or multi-level number storage, the a-Sistructure can be operated via a method that switches it between the ONand OFF states discussed above. This can be done by applying a voltageacross the a-Si structure, wherein the applied voltage has a magnitudeand duration that are selected so as to achieve a predeterminedprobability of the a-Si device switching from the OFF state to the ONstate. The predetermined probability of successful switching can be, forexample, 95% or can be any other percentage desired or required for aparticular application of the a-Si device.

As indicated above, the successful operation of the a-Si device dependsnot only on the amplitude, but also on the duration time of the bias.The switching control requirements also depend on whether digitalswitching (e.g. as single-bit memories) or analog operations (e.g. asinterconnects) are desired. For the Poissonian processes discussedabove, FIG. 3( c) plots the probability of exactly one switching eventoccurring during time t while FIG. 3( d) plots the probability of atleast one switching event occurring during time t. They correspond tothe case with no external series resistance and a single switching rate1/τ applies to the step-wise filament formation process. It is clearthen that the device acts as an excellent digital switch for long-enoughprogramming pulses (e.g., 95% success rate is achieved for t_(pulse)>3τ). On the other hand, for multi-level number storage or analogoperations of the switch, the pulse width has to be optimized. Forexample, t_(pulse) needs to be centered at τ for the highest probabilitythat only the first switching occurs. Even so, the maximum success rateis only ˜38%, as indicated in FIG. 3( c). However, the success rate formulti-bit operations can be significantly improved by the addition ofthe external series resistance, which dramatically reduces thesubsequent switching rates. FIG. 3( e) plots the probability that onlythe first switching event will occur in a simplified two-step filamentformation process in which two different rates are used:

$\begin{matrix}{{{P(t)} = {\frac{\tau_{2}}{\tau_{1} - \tau_{2}}\left( {^{{- t}/\tau_{1}} - ^{{- t}/\tau_{2}}} \right)}},} & (4)\end{matrix}$

where τ₁=3.36 us and τ₂=1.30 s corresponding to the switching rates whenthe voltage across the device changes from 4V (before the firstswitching event and R>>R_(S)) to 2V (after the first switching event andR=R_(S)) respectively, as a result of the voltage divider effect afterthe first switching event. A much higher success rate of greater than99% can now be achieved for 5τ_(r)<t_(pulse)<0.01τ₂ (about 13 ms timemargin at 4 V bias) to limit the switching to the first event only. Inaddition, similar exhibited characteristics are expected from otherresistive switching devices since many of them involve some sort ofactivation energy process, e.g. the diffusion of ions and the redoxprocesses.

The activation energy of the barriers can be extracted from temperaturedependence of the wait time from Equation 1. FIG. 4( a) shows the timedependent resistance change at zero-bias at temperatures from 100° C. to150° C. for a device originally programmed in the ON state. Withreference back to FIG. 1( c), the sudden transitions to the OFF statecorrespond to the retrieval of the Ag filament by the thermallyactivated hopping of the Ag⁺ particle towards the top electrode from thetrapping site nearest to the bottom electrode, as verified by the goodfitting in the Arrhenius type plot of the wait time t versus 1/k_(B)Tthat is shown in FIG. 4( b). The activation energy for the ON/OFFtransition can be extracted to be 0.87 eV for this device from the slopeof the Arrhenius plot and the retention time at room temperature can beestimated to be 6 years from extrapolation.

When incorporated into memory arrays such as shown in FIG. 6 or whenotherwise necessary or desirable for a particular application, the a-Sidevice can be constructed with an intrinsic diode in the form of a p-njunction. This can be incorporated during fabrication by furtherincluding an n-type layer between the p-type poly-Si electrode and thesecond metal (e.g., platinum) electrode. An example of this is shown inFIG. 7 which can be identical to the a-Si resistive device 10 of FIG. 1except for the added n-type layer under the Pt electrode. When used in amemory array of the crossbar type, this construction can be used toprevent cross-talk between adjacent devices since forward conductingcurrent flowing out of one cell through its diode will be blocked by the(now reverse-biased) diode of the adjacent cell.

FIG. 8 depicts another embodiment of a single cell a-Si resistive device210 that includes a built in diode which can be formed usingconventional CMOS fabrication techniques. Numbered elements of FIG. 8differing by 200 relative to numbered elements of FIG. 1 can havesimilar, although not necessarily identical, constructions and functionsto the numbered elements of FIG. 1. The device 210 can be built up usinga N-type crystalline silicon substrate 222. P-type silicon region 218can be a poly-Si layer formed by conventional CMOS processes such as ionimplantation or diffusion method. The P-type region 218 and Ag terminal212 make contact to a-Si pillar 214 which can change its resistancedepending on applied bias, as described above. Insulating layer 216 canbe formed by SOG (spin-on-glass) or CVD (chemical vapor deposition)methods. A second metal electrode 220 is formed in contact with thesubstrate layer 222, and can be, for example, a TiN/Al metal stack whichhas good electrical contact. Highly doped N-type region 226, which canbe formed by ion implantation, further ensures good electrical contactsbetween N-Sub 222 and the electrode 220. Because P-type layer 218 isbuilt on a N-type silicon substrate 222, they together form a diode.Hence, when the electrodes 212 and 220 are used for external contacts,the entire structure comprises an a-Si resistive device having aseries-connected PN diode. FIG. 9 depicts a structure 310 similar tothat of FIG. 8, with the primary difference being the type of startingsubstrate which can be a p-type substrate 318. In this case, N-typeregion 222 is then formed on the substrate 218 (by ion implantation ordiffusion methods), which again gives the a-Si resistive device aseries-connected PN diode.

FIG. 10 depicts one exemplary implementation of an a-Si resistive device400 that includes some of the control circuitry used to program the a-Sistructure to any of a number of different resistances to thereby permitmultiple bit or other multi-level number storage in the device. Thisstructure 400 that can be built by conventional CMOS fabricationprocesses. The structure combines an a-Si resistive device 402 (with PNdiode) and a FET 404 that can act as a gate bias controlled resistor.The a-Si device 402 includes an a-Si nanopillar 414 embedded in aninsulating layer 416 beneath of top electrode that can be silver orother suitable metal. The FET 404 includes a gate 430 formed over a gateoxide layer 432. Depending on applied bias at the gate 430, theresistance between two N-type regions 423, 425 can be controlled tothereby create a variable resistor. The N-type region 425 is connectedto the second metal electrode 420 via a highly-doped N-type region 427.The structure 400 can be fabricated on P-type silicon substrate 418.Another P-type region 421 has different resistance value than P-Sub 418to control the device performance. A poly-Si interconnection 450 bridgesthe a-Si resistive device 402 and the N-type FET 404 by connecting twoN-type regions 422, 423. STI (shallow trench isolation) 440 is astandard CMOS fabrication technique which can suppress direct leakagecurrent though the P-Sub 418. If the thickness of the active substrate(body) is thin (<1 um), then the structure of device 400 can besimplified as shown in FIG. 11. This essentially involves removingelements 440, 450, and 423 from the device 400 of FIG. 10. The substrate518 can be P-type Silicon. The N type region 522 can serve as an N partfor a PN diode and a part of the FET as well, resulting in compactdevice size.

Apart from the use of an added n-type layer to create a built-in diodeas described above, the basic a-Si resistive device disclosed herein canitself exhibit an intrinsic diode characteristic. FIGS. 12 and 13 depictan example of this diode characteristic. As shown in these figures, whenthe memory device is in its ON state, current can only flow through thedevice at positive bias but not at negative bias. This intrinsic diodecharacteristic can also be used to regulate current flow and preventcrosstalk in crossbar arrays. The intrinsic diode characteristic can beobtained by controlling the a-Si deposition conditions and/or bycontrolling the programming current. Without wishing to being limited toany particular theory of operation, it is believed that the probablecause of this intrinsic characteristic is a built-in electric field atthe interface, and/or a shallow trap potential between PECVDa-Si/poly-Si. Naturally retracted Ag-mobile ions can be again injectedto the close interface with much smaller bias than the usual programmingbias so when reading the device state with a small positive read voltagean ON state can still be obtained. This process is different from theerase process in which Ag mobile ion retracted to another stableposition with sufficient barrier energy.

It is to be understood that the foregoing is a description of one ormore preferred exemplary embodiments of the invention. The invention isnot limited to the particular embodiment(s) disclosed herein, but ratheris defined solely by the claims below. Furthermore, the statementscontained in the foregoing description relate to particular embodimentsand are not to be construed as limitations on the scope of the inventionor on the definition of terms used in the claims, except where a term orphrase is expressly defined above. Various other embodiments and variouschanges and modifications to the disclosed embodiment(s) will becomeapparent to those skilled in the art. All such other embodiments,changes, and modifications are intended to come within the scope of theappended claims.

As used in this specification and claims, the terms “for example”, “forinstance”, “such as”, and “like”, and the verbs “comprising”, “having”,“including”, and their other verb forms, when used in conjunction with alisting of one or more components or other items, are each to beconstrued as open-ended, meaning that the listing is not to beconsidered as excluding other, additional components or items. Otherterms are to be construed using their broadest reasonable meaning unlessthey are used in a context that requires a different interpretation.

1. A non-volatile solid state resistive device, comprising: a firstelectrode; a p-type silicon second electrode; and a non-crystallinesilicon nanostructure electrically connected between said electrodessuch that said nanostructure has a resistance that is adjustable inresponse to a voltage being applied to said nanostructure via saidelectrodes.
 2. A resistive device as defined in claim 1, wherein saidnon-crystalline silicon nanostructure comprises an amorphous siliconnanostructure.
 3. A resistive device as defined in claim 1, wherein saidsilicon second electrode comprises a p-type doped poly-siliconelectrode.
 4. A resistive device as defined in claim 1, wherein saidsilicon nanostructure comprises a pillar having opposed end faces witheach electrode being in contact with a different one of said end faces.5. A resistive device as defined in claim 1, wherein said siliconnanostructure is nanoscale in all three spatial dimensions.
 6. Aresistive device as defined in claim 1, wherein each of said dimensionsis less than 100 nm.
 7. A resistive device as defined in claim 1,further comprising one or more resistive components electricallyconnected in series with said silicon nanostructure.
 8. A resistivedevice as defined in claim 7, wherein said resistive component comprisesa control resistor.
 9. A resistive device as defined in claim 1, furthercomprising a control circuit that includes said one or more resistivecomponents along with circuitry operable to selectively alter the amountof series resistance connected to said silicon nanostructure.
 10. Aresistive device as defined in claim 1, further comprising a controlcircuit operable to adjust the resistance of said silicon nanostructurebetween more than two resistance values.
 11. A resistive device asdefined in claim 10, wherein said control circuit provides a controlresistance connected in series with said silicon nanostructure, saidcontrol circuit being operable to adjust the resistance of the siliconnanostructure to any of the resistance values by setting the controlresistance to an associated resistance value.
 12. A resistive device asdefined in claim 1, further comprising an n-type doped silicon layer incontact with said p-type second electrode such that said resistivedevice includes a diode in series with said silicon nanostructure.
 13. Aresistive device as defined in claim 1, wherein said first electrode isa metal electrode that, in the presence of an applied voltage acrosssaid electrodes, supplies metal ions that form a filament within saidsilicon nanostructure.
 14. A resistive device as defined in claim 13,wherein said first electrode comprises silver.
 15. A resistive device asdefined in claim 13, further comprising a second metal electrode incontact with said p-type silicon electrode at a location near saidsilicon nanostructure.
 16. A resistive device as defined in claim 15,wherein said second metal electrode is spaced from said siliconnanostructure by no more than 100 nm.
 17. A digital non-volatile memorydevice having at least one memory cell that comprises the resistivedevice defined in claim
 1. 18. A memory device as defined in claim 17,wherein the silicon nanostructure of said resistive device is the onlysilicon nanostructure in said memory cell having an adjustableresistance, and wherein the adjustable resistance can be set to any ofthree or more resistances each of which corresponds to a differentstored number, whereby said memory cell is capable of multi-level numberstorage.
 19. A memory device as defined in claim 18, further comprisinga control circuit for setting the adjustable resistance value based on anumber to be stored in the memory cell.
 20. A memory device as definedin claim 19, wherein the control circuit includes a control resistancein series with said silicon nanostructure.
 21. An electronic circuithaving an electrical interconnect that comprises the resistive devicedefined in claim
 1. 22. A non-volatile solid state resistive device,comprising: a first metal electrode; a p-type poly-silicon electrode; aninsulating layer located at least partially between said electrodes; anamorphous silicon structure embedded in said insulating layer and havingopposing end faces each connected to a different one of said electrodes,wherein said first electrode comprises a metal that, in the presence ofan applied voltage across said electrodes, supplies metal ions that forma filament within said silicon structure, whereby said silicon structureexhibits a resistance that can be adjusted based on the applied voltage;and a second metal electrode in contact with said poly-silicon electrodeat a location that is no more than 100 nm from said silicon structure.23. A resistive device as defined in claim 22, wherein said insulatinglayer comprises a spin-on-glass layer.
 24. A method of adjusting theresistance of a non-volatile solid state resistive device from abeginning resistance value to a final resistance value, comprising thesteps of: electrically connecting the non-volatile solid state resistivedevice in series with a second resistive device having a resistanceselected based on the final resistance value; and applying a voltageacross the series-connected resistive devices.
 25. The method of claim24, wherein said applying step further comprises setting the finalresistance value based at least in part on the magnitude of the appliedvoltage, the duration of the applied voltage, or both.
 26. The method ofclaim 24, wherein said applying step further comprises setting the finalresistance value by applying a voltage of a selected magnitude andduration across the series-connected resistive devices.
 27. The methodof claim 24, wherein the final resistance value is one of a plurality ofselectable resistance values and wherein the step of electricallyconnecting the resistive devices further comprises electrically formingthe second resistive device by selectively inserting or shunting one ormore control resistors in series with the non-volatile solid stateresistive device based on a chosen one of the selectable resistancevalues.
 28. The method of claim 24, further comprising the step ofresetting the non-volatile solid state resistive device to the beginningresistance value by applying an opposite-polarity reset voltage to thenon-volatile solid state resistive device.
 29. A method of adjusting anon-volatile solid state switching device from an OFF state to an ONstate, comprising the step of applying a voltage across anon-crystalline silicon nanostructure, wherein the applied voltage has amagnitude and duration that are selected so as to achieve apredetermined probability of the silicon nanostructure switching fromthe OFF state to the ON state.
 30. The method of claim 29, wherein theapplying step further comprises the step of forming a conductivefilament within the non-crystalline silicon nanostructure in response tothe applied voltage.